Memory Interfacing with the 8088/8086/80286 Processor — Part 2 (Advanced Memory Interfacing Example)

In this continuation of our exploration into memory interfacing with the 8088 processor, we delve into a more complex scenario involving the integration of both Read-Only Memory (ROM) and Random Access Memory (RAM) into a single system. This scenario introduces the challenge of interfacing 4KB of ROM and 8KB of RAM, utilizing specific chip models (2716 for ROM and 6116 for RAM), each with distinct starting addresses. This example not only broadens the understanding of memory interfacing but also illustrates how to manage varying memory sizes and types within a system.

Understanding the Memory Chips

The scenario specified requires interfacing 4KB of ROM, using 2716 chips, and 8KB of RAM, using 6116 chips. The numbering of these chips provides insight into their capacity: the last two digits, when divided by 8, indicate the chip’s size in KB. Thus, 2716 ROM chips are 2KB in size, and 6116 RAM chips are also 2KB. To achieve the required memory sizes, we’ll need multiple chips: two for ROM (to make up 4KB) and four for RAM (to total 8KB).

Memory Mapping and Address Allocation

The system design specifies that ROM begins at address 0000, while RAM starts at 0800, introducing non-sequential memory mapping. This requires careful planning to ensure each chip is correctly addressed:

• ROM Interfacing: With two 2KB 2716 ROM chips, the first chip (ROM1) is mapped from 0000 to 07FF, and the second chip (ROM2) from 0800 to 0FFF. This arrangement fills the 4KB ROM requirement.

• RAM Interfacing: Four 6116 RAM chips are needed to provide 8KB of memory, starting from address 0800. Each chip, being 2KB, is allocated a unique 2KB block within the 0800 to 09FF range, ensuring sequential and non-overlapping address spaces for each RAM chip.

Decoding Logic and Address Selection

The core of memory interfacing lies in the decoding logic, which determines which memory chip is selected based on the processor’s address lines. This logic uses address lines A11, A12, and A15 to differentiate between ROM and RAM chips and within their respective groups. The decoder, informed by the binary representation of each chip’s address range, activates the appropriate chip select signals based on the current address.

Implementing the Decoder

A decoder, such as the LS138, interprets the address lines to select the correct memory chip. For ROM chips, lower address lines (A0 to A10) directly address memory locations within the chip, while higher address lines (A11 to A15) are used in decoding to select the chip itself. RAM interfacing follows a similar pattern, with the addition of read/write functionality to accommodate the RAM’s writable nature.

Building the Complete Memory Interfacing Circuit

The interfacing circuit connects the 8088 processor’s system bus, including data, address, and control signals, to the memory chips. Address lines A0 to A10 are shared by all chips for internal addressing, while the decoding logic, driven by higher address lines and implemented through a decoder, manages chip selection. Control signals, specifically the read and write commands, are directed appropriately: read commands to both ROM and RAM, and write commands solely to RAM.

Conclusion

This detailed example of interfacing 4KB of ROM and 8KB of RAM to the 8088 processor highlights the complexity and precision required in memory system design. By carefully mapping memory addresses, designing decoding logic, and connecting the system bus to memory chips, we can build a functional memory system tailored to specific requirements. This process underscores the critical nature of memory interfacing in computer architecture, providing a foundation for further exploration and more sophisticated system designs.